FlexRAN Custom Pathway

From gaining access to the Intel® FlexRAN™ Reference Architecture software packages and documentation, to building and testing the Layer 1 executable, this course outlines all the tasks required to start using the FlexRAN™ Reference Architecture, a reference Layer 1 RAN software that is optimized to run efficiently on Intel architecture and is 3GPP compliant. While this course demonstrates key steps of the installation process, it is very important to remember to refer to the newest documentation as the commands shown in this video may not be current to the newest release.​

L1 Forward Error Correction (FEC) workloads in Intel® FlexRAN™ Reference Architecture can be offloaded using one of two types of Intel hardware acceleration products: Intel® FPGA Programmable Acceleration Cards (Intel® FPGA PAC) and Intel® vRAN Dedicated Accelerator ACC100. Learn more about FEC Programmable Accelerated Cards (PAC) and how they significantly increase the cell capacity and performance of second generation Intel® Xeon® Scalable processors and Intel Xeon D processors running RAN L1 workloads.

The Intel® FlexRAN™ Reference Architecture SDK provides low-level wireless signal processing modules optimized for use on Intel® architecture platforms. This course provides an overview of SDK, the SDK Module level structure and testbench and SDK Optimization tools and resources.

This course introduces Intel® FlexRAN™ Reference Architecture 5GNR CU-UP architecture. Hear an overview of the Intel FlexRAN Reference Architecture L2+, learn about the benefits of FD.io VPP and gain an understanding of the Intel FlexRAN software CU-UP Architecture.

The Intel® FlexRAN™ Reference Architecture layer 1 (L1) PHY application takes radio signals from the RF front-end and provides real-time signal and physical layer processing on servers built with Intel® Xeon® Scalable processors and Intel® Xeon® D processors. Learn the details about each pipeline design.

In this course, you’ll learn about Intel® FlexRAN™ Reference Architecture L2 DU layer as well as the L2 DU buffer management.

Learn more about end-to-end (E2E) integration based on Intel® FlexRAN™ Reference Architecture. This course provides an overview of 5G E2E Topology and gNB architecture, introduces PHY layer configuration files and discusses debug methods and tools provided during E2E testing.

Learn how to enable Intel® FlexRAN™ Reference Architecture stack in container environments. The course would cover basic concepts, plugins of k8s and practice to deploy Intel FlexRAN reference architecture in a container environment.

BBU Pooling is adopted as the framework of Intel® FlexRAN™ Reference Architecture L2+ reference library. In this course, there will be a brief introduction to the Intel FlexRAN reference architecture and how Intel FlexRAN technology uses of BBU Pooling Framework. The discussion will cover the focus, objectives, tasks and architecture of the BBU Pooling Framework.

What is the Intel® FlexRAN™ Reference Architecture and what is its current scope? How is the Intel FlexRAN Reference Architecture pipeline built and how can it be verified? To learn why Intel has invested in Intel FlexRAN technology and to hear the answers to these questions, view this course.