Program Overview
Courses in this pathway discuss Intel L1+L2 reference design on x86 platforms, including packet processing optimization and how to implement wireless access loads with Intel® FlexRAN™ Reference Architecture and Intel® AVX-512 instruction set. Content is Intel Confidential, subject to the terms of the CNDA and must not be disclosed to any 3rd party.
5 Courses
Share With
The Intel® FlexRAN™ Reference Architecture SDK provides low-level wireless signal processing modules optimized for use on Intel® architecture platforms. This course provides an overview of SDK, the SDK Module level structure and testbench and SDK Optimization tools and resources.
The Intel® FlexRAN™ Reference Architecture layer 1 (L1) PHY application takes radio signals from the RF front-end and provides real-time signal and physical layer processing on servers built with Intel® Xeon® Scalable processors and Intel® Xeon® D processors. Learn the details about each pipeline design.
Learn more about end-to-end (E2E) integration based on Intel® FlexRAN™ Reference Architecture. This course provides an overview of 5G E2E Topology and gNB architecture, introduces PHY layer configuration files and discusses debug methods and tools provided during E2E testing.
BBU Pooling is adopted as the framework of Intel® FlexRAN™ Reference Architecture L2+ reference library. In this course, there will be a brief introduction to the Intel FlexRAN reference architecture and how Intel FlexRAN technology uses of BBU Pooling Framework. The discussion will cover the focus, objectives, tasks and architecture of the BBU Pooling Framework.
What is the Intel® FlexRAN™ Reference Architecture and what is its current scope? How is the Intel FlexRAN Reference Architecture pipeline built and how can it be verified? To learn why Intel has invested in Intel FlexRAN technology and to hear the answers to these questions, view this course.